that's scaling fast. Position: Senior FPGA Engineer Location: Cambridge Salary: £60-120k Key Skills: FPGA, Verilog or VHDL

, software, and physics teams. Desirable Core Requirements FPGA development experience using VHDL or Verilog on Xilinx FPGAs

Experience with GnuRadio or similar SDR platforms. FPGA/RFSOC development experience and proficiency in VHDL or Verilog

is required for Staff level. -Working knowledge of Verilog-AMS modelling, MATLAB and Python is a bonus. Familiar with the use

-architectural specs which work through the design problems before coding (System Verilog, Verilog). Preferred Qualifications

to system level - Proficiency in System Verilog - Experience in identifying and resolving complex design and verification... tools and scripting languages (Python or Perl) for automation - System Verilog coding and debug Amazon is an equal

, Microsemi (Actel) or Lattice and their tools. Advancedverification techniquesusing eitherVHDLorSystem Verilog/ UVM. Specifying

, communication systems, high-speed digital interfaces, and payload data path architecture. Proficiency with VHDL, Verilog

: 10+ years of hands-on FPGA development experience Strong RTL design and verification using SystemVerilog, Verilog

, ideally up to SIL4. Hands-on experience with modern microcontroller SDKs. Knowledge of FPGA design (VHDL/Verilog) and CPLD

, ideally up to SIL4. Hands-on experience with modern microcontroller SDKs. Knowledge of FPGA design (VHDL/Verilog) and CPLD

working with more than one language - VHDL, Verilog, SystemVerilog The successful Candidate must currently hold or be able

, ARM processors, GPUs and microcontrollers (typically using VHDL or Verilog) Designing signal processing algorithms

and firmware using industry-standard simulation tools. Experience with Verilog, SystemVerilog, C, and C++. Experience developing

using Verilog or SystemVerilog Experience designing complex digital IP, SoCs or CPU subsystems Knowledge of on-chip

design/architecture Verification Test bench architecture with System Verilog or C++ Verification Methodology: Advanced...: Mentor Graphics Modelsim / Questasim Digital electronic design in hardware development languages: VHDL and either Verilog

and forward-thinking approach. Skills & Experience We Value Familiarity with Verilog/SystemVerilog, OSVVM, UVM or UVVM

systems Experience of digital design (EDA tools, Verilog, VHDL) ACADEMIC CREDENTIALS: Bachelor’s, Master's or PhD

and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge

synthesis, STA, UPF (low power design) and DfT Proficiency in HDLs like System Verilog or VHDL Strong know-how in C